//--------------------------------------------------------------------------------------------
//
//
//      Component name  : fpadd
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPadd(ADD_SUB, FP_A, FP_B, clk, FP_Z,IVLD,OVLD);
   input         ADD_SUB;
   input [31:0]  FP_A;
   input [31:0]  FP_B;
   input         clk;
   output [31:0] FP_Z;
   input         IVLD;
   output        OVLD;

   wire           OVLD;
   
   
   wire          ADD_SUB_out;
   wire [7:0]    A_EXP;
   wire          A_SIGN;
   wire          A_SIGN_stage2;
   wire          A_SIGN_stage3;
   wire [28:0]   A_align;
   wire [28:0]   A_in;
   wire          A_isINF;
   wire          A_isNaN;
   wire          A_isZ;
   wire [7:0]    B_EXP;
   wire          B_XSIGN;
   wire          B_XSIGN_stage2;
   wire          B_XSIGN_stage3;
   wire [28:0]   B_align;
   wire [28:0]   B_in;
   wire          B_isINF;
   wire          B_isNaN;
   wire          B_isZ;
   wire [7:0]    EXP_base;
   wire [7:0]    EXP_base_stage2;
   wire [8:0]    EXP_diff;
   wire [7:0]    EXP_norm;
   wire          OV;
   wire          OV_stage4;
   wire [27:0]   SIG_norm;
   wire [27:0]   SIG_norm2;
   wire [7:0]    Z_EXP;
   wire          Z_SIGN;
   wire          Z_SIGN_stage4;
   wire [28:0]   add_out;
   wire          cin;
   wire          cin_sub;
   wire          invert_A;
   wire          invert_B;
   wire          isINF_tab;
   wire          isINF_tab_stage2;
   wire          isINF_tab_stage3;
   wire          isINF_tab_stage4;
   wire          isNaN;
   wire          isNaN_stage2;
   wire          isNaN_stage3;
   wire          isNaN_stage4;
   wire          isZ_tab;
   wire          isZ_tab_stage2;
   wire          isZ_tab_stage3;
   wire          isZ_tab_stage4;
   wire          zero;
   wire          zero_stage4;
   
   
   FPadd_stage1 I1(/*AUTOINST*/
		   // Outputs
		   .ADD_SUB_out		(ADD_SUB_out),
		   .A_EXP		(A_EXP[7:0]),
		   .A_SIGN		(A_SIGN),
		   .A_in		(A_in[28:0]),
		   .A_isINF		(A_isINF),
		   .A_isNaN		(A_isNaN),
		   .A_isZ		(A_isZ),
		   .B_EXP		(B_EXP[7:0]),
		   .B_XSIGN		(B_XSIGN),
		   .B_in		(B_in[28:0]),
		   .B_isINF		(B_isINF),
		   .B_isNaN		(B_isNaN),
		   .B_isZ		(B_isZ),
		   .EXP_diff		(EXP_diff[8:0]),
		   .cin_sub		(cin_sub),
		   // Inputs
		   .ADD_SUB		(ADD_SUB),
		   .FP_A		(FP_A[31:0]),
		   .FP_B		(FP_B[31:0]),
		   .clk			(clk));
   
   FPadd_stage2 I2(/*AUTOINST*/
		   // Outputs
		   .A_SIGN_stage2	(A_SIGN_stage2),
		   .A_align		(A_align[28:0]),
		   .B_XSIGN_stage2	(B_XSIGN_stage2),
		   .B_align		(B_align[28:0]),
		   .EXP_base_stage2	(EXP_base_stage2[7:0]),
		   .cin			(cin),
		   .invert_A		(invert_A),
		   .invert_B		(invert_B),
		   .isINF_tab_stage2	(isINF_tab_stage2),
		   .isNaN_stage2	(isNaN_stage2),
		   .isZ_tab_stage2	(isZ_tab_stage2),
		   // Inputs
		   .ADD_SUB_out		(ADD_SUB_out),
		   .A_EXP		(A_EXP[7:0]),
		   .A_SIGN		(A_SIGN),
		   .A_in		(A_in[28:0]),
		   .A_isINF		(A_isINF),
		   .A_isNaN		(A_isNaN),
		   .A_isZ		(A_isZ),
		   .B_EXP		(B_EXP[7:0]),
		   .B_XSIGN		(B_XSIGN),
		   .B_in		(B_in[28:0]),
		   .B_isINF		(B_isINF),
		   .B_isNaN		(B_isNaN),
		   .B_isZ		(B_isZ),
		   .EXP_diff		(EXP_diff[8:0]),
		   .cin_sub		(cin_sub),
		   .clk			(clk));
   
   FPadd_stage3 I3(/*AUTOINST*/
		   // Outputs
		   .A_SIGN_stage3	(A_SIGN_stage3),
		   .B_XSIGN_stage3	(B_XSIGN_stage3),
		   .EXP_base		(EXP_base[7:0]),
		   .add_out		(add_out[28:0]),
		   .isINF_tab_stage3	(isINF_tab_stage3),
		   .isNaN_stage3	(isNaN_stage3),
		   .isZ_tab_stage3	(isZ_tab_stage3),
		   // Inputs
		   .A_SIGN_stage2	(A_SIGN_stage2),
		   .A_align		(A_align[28:0]),
		   .B_XSIGN_stage2	(B_XSIGN_stage2),
		   .B_align		(B_align[28:0]),
		   .EXP_base_stage2	(EXP_base_stage2[7:0]),
		   .cin			(cin),
		   .clk			(clk),
		   .invert_A		(invert_A),
		   .invert_B		(invert_B),
		   .isINF_tab_stage2	(isINF_tab_stage2),
		   .isNaN_stage2	(isNaN_stage2),
		   .isZ_tab_stage2	(isZ_tab_stage2));
   
   FPadd_stage4 I4(/*AUTOINST*/
		   // Outputs
		   .EXP_norm		(EXP_norm[7:0]),
		   .OV_stage4		(OV_stage4),
		   .SIG_norm		(SIG_norm[27:0]),
		   .Z_SIGN_stage4	(Z_SIGN_stage4),
		   .isINF_tab_stage4	(isINF_tab_stage4),
		   .isNaN_stage4	(isNaN_stage4),
		   .isZ_tab_stage4	(isZ_tab_stage4),
		   .zero_stage4		(zero_stage4),
		   // Inputs
		   .A_SIGN_stage3	(A_SIGN_stage3),
		   .B_XSIGN_stage3	(B_XSIGN_stage3),
		   .EXP_base		(EXP_base[7:0]),
		   .add_out		(add_out[28:0]),
		   .clk			(clk),
		   .isINF_tab_stage3	(isINF_tab_stage3),
		   .isNaN_stage3	(isNaN_stage3),
		   .isZ_tab_stage3	(isZ_tab_stage3));
   
   FPadd_stage5 I5(/*AUTOINST*/
		   // Outputs
		   .OV			(OV),
		   .SIG_norm2		(SIG_norm2[27:0]),
		   .Z_EXP		(Z_EXP[7:0]),
		   .Z_SIGN		(Z_SIGN),
		   .isINF_tab		(isINF_tab),
		   .isNaN		(isNaN),
		   .isZ_tab		(isZ_tab),
		   .zero		(zero),
		   // Inputs
		   .EXP_norm		(EXP_norm[7:0]),
		   .OV_stage4		(OV_stage4),
		   .SIG_norm		(SIG_norm[27:0]),
		   .Z_SIGN_stage4	(Z_SIGN_stage4),
		   .clk			(clk),
		   .isINF_tab_stage4	(isINF_tab_stage4),
		   .isNaN_stage4	(isNaN_stage4),
		   .isZ_tab_stage4	(isZ_tab_stage4),
		   .zero_stage4		(zero_stage4));
   
   FPadd_stage6 I6(/*AUTOINST*/
		   // Outputs
		   .FP_Z		(FP_Z[31:0]),
		   // Inputs
		   .OV			(OV),
		   .SIG_norm2		(SIG_norm2[27:0]),
		   .Z_EXP		(Z_EXP[7:0]),
		   .Z_SIGN		(Z_SIGN),
		   .clk			(clk),
		   .isINF_tab		(isINF_tab),
		   .isNaN		(isNaN),
		   .isZ_tab		(isZ_tab),
		   .zero		(zero));



reg    [7:0]      ivld_dly  = 'd0 ;
always @ (posedge clk )
begin
	ivld_dly <= {ivld_dly[6:0],IVLD};
end
assign   OVLD = ivld_dly[5] ;


endmodule
